Design of a high-performance and flexible processor for modern HPC

High Performance Computing (HPC) is rapidly evolving today. Extraction of knowledge from big data through Deep Neural Networks (DNNs) is a new type of workload which adds on top of the traditional workload for HPC, i.e., data centre-based computation for mainly modelling and simulation.

This new AI-focused workload acts as a new driver for evolution of HPC architecture. While the focus of traditional HPC has been primarily manipulating double-precision floating points to express complex systems, the new workload also requires reduced-precision processing. This new design should be in line with advanced computing trend which is 10 times performance improvement every 4 years and 10 times energy efficiency improvement every 4 years (source: Top500). This requires specially designed processors for different tasks to maximise efficient use of transistors for the applications. A profound solution for this demand for a higher computational performance is heterogeneity, i.e., generic processing interfaced with different accelerators, designed with low power consumption in mind.

Two main challenges of today’s HPC are extensive use of power-hungry GPUs and closed source designs. Fortunately, with the introduction of open-source RISC-V architecture, there is currently massive research and development based on this architecture for various performance and power efficient designs targeting different applications. The number of chips that include at least some RISC-V technology is expected to grow 73.6% per year through 2027, mainly due to AI demands¹. Our long-term plan is to develop a new HPC ecosystem including both hardware and software with the intention of making resources available to public and private users. This requires development of a common platform, general purpose processor, and accelerators. The accelerators will be RISC-V based and include components designed for different types of operations, such as vector processing, tensor accelerating, and multi-precision processing. The design can be tailored to address the needs of IoT and automotive sector as well.

This PhD is a part of our larger HPC design initiative. The modern processor designs for machine learning operations, such as Google’s Tensor Processing Unit (TPU) contain a large systolic array structure designed for massively parallel matrix multiply-and-add operations. This unit is interfaced with a host processor for controlling operations. The main drawback of these designs is the fixed precision format specified for data items of operations in matrix multiplier unit. As the format and the number of bits assigned for each data item have a significant impact on the performance but lower impact on the accuracy, it should be up to the programmer to strike a balance between performance and accuracy for their applications. Therefore, this PhD focuses on the development of a novel RISC-V based processor specifically designed to be adjustable for various precisions of machine learning operations. This flexibility in precision should be introduced in both processor design and high-level programmer level. A new extended RISC-V core will be developed to support the variable precision with custom Instruction Set Architecture (ISA) extension for supporting the added flexibility. A software stack will later be developed for this architecture (by another software developer) to develop LLVM based C compiler and the required libraries for multi-precision programming.

Supervisors

Primary supervisor: Dr Sam Amiri

Secondary supervisor: Dr Luciano Ost

Entry requirements for United Kingdom

Successful applicants should have, or expect to achieve, an undergraduate honours degree with a minimum classification of a 2:1, or equivalent in a relevant subject for the PhD topic. A relevant master’s degree and/or experience would also be advantageous.

English language requirements

Applicants must meet the minimum English language requirements. Further details are available on the International website.

How to apply

All applications should be made online. Under programme name, select ‘Electronic, Electrical and Systems Engineering’. Please quote reference number: P1SAM23-12 in your application. 

Competition for funded entry is high so please ensure that you submit a CV and the minimum supporting documents by the advert closing date. Failure to do so will mean that your application will not be taken forward for consideration. See studentship assessment criteria.

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