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DynaRISC - a RISC Multicore Processor with Dynamically Reconfigurable Fine-grained Embedded Fabrics

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  • Full or part time
    Dr D Koch
  • Application Deadline
    Applications accepted all year round
  • Competition Funded PhD Project (Students Worldwide)
    Competition Funded PhD Project (Students Worldwide)

Project Description

The progress in silicon manufacturing allows the integration of a billion and more transistors on a single die. This theoretically allows fitting hundreds of CPU cores on a single chip. However, by shrinking CMOS feature sizes towards the nanometer range, power density and reliability are now the major technology drivers. Consequently, the question is not how many functional units can fit on a chip, but how many functional units can be powered according to a given power budget. Similarly, there is the question how reliable functional units can be produced and operated under device ageing effects.

As a solution to this problem, fine grained reconfiguration shall be examined in this PhD project to gain power efficiency and reliability in multicore processors. The idea is to add a fine-grained reconfigurable area parallel to the ALUs of a multicore processor for accelerating small loop kernels and functions.

Furthermore, the reconfigurable part can be used as a redundant functional unit to mask production defects or aging effects, hence enhancing yield and reliability.

Funding Notes

This School has two PhD programmes: the Centre for Doctoral Training (CDT) 4-year programme and a conventional 3-year PhD programme.

School and University funding is available on a competitive basis.


The minimum requirements to get a place in our PhD programme are available from:

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FTE Category A staff submitted: 44.86

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