Efficient On-Chip Communications in the Manycore Era

With the relentless advance in electronic miniaturisation we have reached a point in which we are incapable of increasing processor performance by means of traditional ways: in the one hand, all significant microarchitectural improvements are already in place and, in the other hand, clock frequency has reached the limits imposed by the power and dissipation capabilities of current technology.

For this reason, the microprocessor community has been forced to move towards multicore architectures with increasingly high number of processing cores. As the number of cores increases, established on-chip communication infrastructures (buses) start to become a performance bottleneck because a centralised, shared medium results on increases of power consumption and transmission latency as well as in decreases of per-core available bandwidth. For this reason, decentralised infrastructures (networks on chip) are gaining importance and will be essential once a critical number of cores is reached. This project aims to investigate such infrastructures in a holistic manner: covering several areas of opportunity (router microarchitecture, interfaces, network topology) and considering different figures of merit (performance, power, area, fault tolerance).