About the Project
Co-supervisor Dr Mark Vousden
POETS - Partial Ordered Event Triggered Systems - technology is based on the idea of an extremely large number (millions) of small cores, embedded in a fast, bespoke, hardware, parallel communications infrastructure - the core mesh. Inter-core communication is asynchronous, and effected by small, fixed size, hardware data packets (a few bytes) - messages. For an important set of industrial problems, POETS architectures are capable of delivering orders of magnitude speed increases at significantly lower power levels. This project is about accelerating a simulation application using POETS.
Moore’s Law is the observation that, on a dense integrated circuit, the number of transistors doubles every two years. While this pace has slowed since the original observation in 1965, reducing the size of devices is still a strong design constraint, along with reducing the power required to operate them.
Regarding data storage in computers, hard drives magnetise regions of the space either "up" or "down" into magnetised domains. Spintronics research over the last decade has realised several alternative potential data carriers, such as skyrmions and magnons, which are both considerably smaller in size, and require less energy to drive through a material. If these properties can be exploited, the size and power requirements of devices can be reduced considerably. The micromagnetic model (a mathematical model) can be used to simulate spintronic devices. However, present computing technology imposes a practical restriction on the size of these models, restricting the scope for designing these devices.
The objective of this project is to develop an application for POETS to perform micromagnetic simulations of these potential data carriers (skyrmions and magnons), which in turn will inform the design of spintronic devices.
If you wish to discuss any details of the project informally, please contact Dr Mark Vousden or Professor Andrew Brown, Sustainable Electronic Technologies (SET)Research Group, Email: [Email Address Removed] / [Email Address Removed] Tel: +44 (0) 2380 593374
A very good undergraduate degree (at least a UK 2:1 honours degree, or its international equivalent).
Closing date: applications should be received no later than 31 August 2020 for standard admissions, but later applications may be considered depending on the funds remaining in place.
Funding: This 3.5 year studentship covers UK tuition fees and provides an annual tax-free stipend at the standard EPSRC rate, which is £15,009 for 2019/20.
Applicants must be UK residents with no restrictions on how long they can stay in the UK and have lived here for at least 3 years prior to the start of the studentship. This residence cannot be mainly for the purpose of receiving full-time education
How To Apply
Applications should be made online here selecting “PhD Electrical and Electronic Engineering (Full time)” as the programme. Please enter Andrew Brown under the proposed supervisor.
Applications should include:
Two reference letters
Degree Transcripts to date
Apply online: https://www.southampton.ac.uk/courses/how-to-apply/postgraduate-applications.page
For further information please contact: [Email Address Removed]
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