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Fault Tolerant design using the PAnDA Device


About This PhD Project

Project Description

The programmable analogue and digital array (PAnDA) device is a multi-reconfigurable chip that consists of an array of configurable circuit blocks interconnected using a programmable routing structure. The term “multi-reconfigurable” refers to PAnDA’s novel and unique feature to access its reconfiguration facilities on multiple design abstraction levels, each effectively representing a different granularity of the architecture. The highest configuration level makes PAnDA compatible to commercial FPGAs in the sense that logic functions can be mapped to configurable logic blocks. In addition to that—and beyond the capabilities of any FPGA currently available—PAnDA can be configured on additional lower levels offering increasingly finer-grained configuration options all the way down to re-sizing individual transistors, which represent the lowest level of design. This project will focus on using PAnDA devices in systems that require high levels of reliability and by making use of the multi-reconfigurable facilities available on PAnDA to create novel fault tolerant mechanisms and procedures.

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