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Guaranteeing Reliability for IoT Edge Computing Systems


Department of Computer Science

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Dr V Pavlidis Applications accepted all year round Competition Funded PhD Project (European/UK Students Only)

About the Project

pical IoT Edge devices collect data from several sensors and may also control several actuators depending on the target application. The data related to these sensors and actuators undergo some processing and are often augmented with security features if the date is of sensitive nature. After this lightweight processing, data is typically transferred to the Cloud for further processing and analysis. Data rates for IoT domains, such as industrial and structure monitoring can be considerably high due to the nature of these applications.
Consequently, the electronics supporting these applications have considerably "on times," a system feature that places high stress on the circuits, thereby accelerating reliability degradation mechanisms, such as aging due to Bias Temperature Instability (BTI) [1], [2] and Hot Carrier Injection (HCI) [3]. This project, therefore, will focus on developing design techniques and circuits to mitigate these issues without degrading performance. The idea is to approach this well-known issue by considering the specific characteristics of IoT applications rather than developing solutions in isolation as has been done to date. The developed methods will be prototyped on an FPGA device to experimentally evaluate their efficiency [4], [5].
The student will develop deep understanding of the reliability mechanisms in integrated circuits, which have increased in importance due to the envisioned applications and the gigascale density of nanoscale feature devices in modern integrated systems. In addition, the student will acquaint herself with the IoT world and will gain solid knowledge in IC design tools. This project is ideal for students who desire to pioneer the design of tomorrow’s IoT Edge devices.

Funding Notes

iCASE ARM IoT

References

[1]. R. Vattikonda, W. Wang, and Y. Cao, "Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design," Proceedings of the IEEE/ACM Design Automation Conference, pp. 1047-1052, July 2006.
[2]. W. Wang et al., "The Impact of NBTI on the Performance of Combinational and Sequential Circuits," Proceedings of the IEEE/ACM Design Automation Conference, pp. 364-369, June 2007.


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