About the Project
The telescopes used for Radio Astronomy generate enormous amounts of data. Processing this data is a very challenging computational problem. For extremely large telescopes like the Square Kilometer Array (SKA), the generated data rate will be so high that storing the data is not possible. This means data needs to be processed in real time.
One of the challenging science problems in radio astronomy is the search and timing of pulsars.
Pulsars are rotating neutron stars that cannot be seen, but send out electromagnetic pulses with a very stable frequency. This makes them very precise clocks, but also helps to study the physical properties of other objects, including black holes, gravitational waves and general relativity.
When a pulsar is in a binary system with another pulsar or a black hole, the two objects are orbiting with a certain frequency. Such systems are extremely interesting to study from a science point of view, but difficult to detect due to the Doppler shift of the pulsating frequency due to the orbiting movement of the pulsar.
A related problem to pulsar search is the observation and characterisation of Fast Radio Bursts (FSB), with similar signals as coming from pulsars, but non-periodic.
Proposed methods to search for unknown pulsars are based on brute force approaches, where the telescope data is processed assuming wide ranges of possible parameters. These parameters include: position in the sky, distance from Earth, pulse period and orbiting period.
In this project we will investigate and implement novel signal processing methods for the search and timing of pulsars and fast radio bursts. The targetted hardware will be high performance computers (HPC) and acceleration boards, in particular FPGAs. Focus will be on novel and efficient parallel algorithms and hence high level approaches will be used in the implementation. For FPGAs this will be High Level Synthesis (HLS) for example OpenCL.
Useful knowlege and skills are
- parallel computing
- parallel programming
- basic astronmy
- hardware design
The research will be undertaken in the Parallel and Reconfigurable Computing lab.
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