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Implementation of soft-input, soft-output detectors and decoders using FPGA

  • Full or part time
  • Application Deadline
    Applications accepted all year round
  • Self-Funded PhD Students Only
    Self-Funded PhD Students Only

About This PhD Project

Project Description

Many emerging and current wireless communication standards, such as LTE and 5G New Radio, use iteratively-decoded error correcting codes, such as turbo-codes and LDPC, based on soft-input, soft-output (SISO) component decoders. Moreover iterative techniques can be used to improve the performance of other functions, such as detectors and equalisers, and hence SISO detectors/equalisers may also be required. However SISO decoders may be complex and expensive to implement. The project will develop implementations of such components using field programmable gate arrays (FPGA), focusing firstly on minimising the gate count required, and secondly on maximising speed.

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