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Novel III-V CMOS logic for large (1 Mbit) ULTRARAM™ arrays

  • Full or part time
  • Application Deadline
    Applications accepted all year round
  • Awaiting Funding Decision/Possible External Funding
    Awaiting Funding Decision/Possible External Funding

About This PhD Project

Project Description

Universal memory combines the best features of DRAM and flash, i.e. is non-volatile, low-voltage, non-destructively read, fast, cheap and high endurance. Implemented as RAM, such a memory would improve datacentre efficiency and allow instantly on/off boot-free computers and devices, with consequent reductions in power consumption. We recently demonstrated novel III-V compound semiconductor candidate universal memory cells (ULTRARAM™), and research is rapidly progressing towards device scaling, fabrication of small arrays and implementation on Si substrates. The objective of this project is to develop and implement the III-V CMOS logic that will enable addressing of bits in large arrays (up to 1 Mbit). It will be suitable for someone with an interest in semiconductor device physics or electronic engineering.

The Physics Department is holder of Athena SWAN Silver award and JUNO Championship status and is strongly committed to fostering diversity within its community as a source of excellence, cultural enrichment, and social strength. We welcome those who would contribute to the further diversification of our department.

Please contact Prof Manus Hayne () for any additional enquiries. You can also apply directly at stating the title of the project and the name of the supervisor.

Closing Date
Applications will be accepted until the post is filled

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