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Platforms for high power RF technology through developing semi-insulating SiC epitaxy.

   School of Engineering

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  Dr V Shah  Applications accepted all year round  Funded PhD Project (UK Students Only)

About the Project

This studentship is to research and develop an exciting fundamental aspect of Silicon Carbide materials for high power RF devices.

This studentship will be supervised by Dr Shah ( at the PEATER group at Warwick University (UK). This project progresses work funded by the Compound Semiconductor Hub (

Silicon Carbide (SiC) is an attractive proposition for the development of efficient, robust power electronic devices, with commonplace devices only introduced into the market within the last 5 years. Early adoption of SiC devices in a number of power conversion applications, including photovoltaic inverters and hybrid and fully-electric cars, have led to the prediction that the SiC power device market will be worth $2bn by 2024. Whilst the high voltage area is obvious to the future of SiC, it’s frequency capability is only assumed to be low (< 500 MHz). There is a serious application of wireless power transmission within the lower part of the RF energy spectrum, in the 1MHz to 3GHz range and in the >50V 1kW+ application space which could be utilised if SiC platforms are developed.

The aim for this studentship would be to develop semi-insulating doping in both 4H-SiC homoepitaxy and 3C-SiC on Si heteroepitaxy, using the UK’s only industrial SiC CVD at the University of Warwick, for use as a platform for RF devices. Certain elemental species in SiC are amphoteric where only low levels (<1e17cm-3) can create semi-insulating (SI) layers (ρ >1e9 Ω-cm). The reasoning for this is to increase the monolithic integration of RF and power electronics both Si and SiC commercial substrates. This would fit into the research priority of “Manufacturing of compound semiconductors (CS) and CS on Silicon (epitaxy, fabrication and process control).”

Specifically in this studentship, both implantation and epitaxy of amphoteric will be developed, in order to demonstrate semi-insulating SiC materials. The student will learn epitaxy, materials characterisation, device simulation and device fabrication. They will design experiments and process samples in our epitaxial and cleanroom facility, which includes state-of-the-art thin film deposition, atomic layer deposition, annealing furnaces, and lithographic facilities. They will also learn characterisation techniques such as electrical measurements (e.g. IV, CV, Hall measurement, DLTS, high voltage measurements), physical measurements (e.g. SEM, TEM, AFM, XRD). Indeed, they may also help to develop new characterisation techniques like c-AFM or XRT with partners or using national facilities (e.g. Diamond Light Source).

The PEATER group has built up a strong international reputation in the field of SiC power electronics for research, innovation and industrial collaboration. The group consists of 8 academics (including Dr Shah) whose research spans materials, devices fabrication, device simulation, packaging, reliability testing, gate driver and converter design, applications and even grid level research. The group are leaders of the Devices and Reliability Themes within the €6.77 million EPSRC Underpinning Power Electronics project. The group has had a wide portfolio of projects concerning SiC technology and device development, e.g. the £16m ESCAPE (from APC-12), £30m @Future BEV (from APC-15), SiCER (£300k, Innovate UK), HubNet (€6.5m), and VESI (€4.2) which are all concerned with SiC MOSFET and PiN diode development with breakdown voltage ranges from 3.3 kV to 10 kV and beyond. Within these projects, Dr Shah is developing growth and characterisation methodology for material suitable for >10 kV power devices. The accumulated knowledge from these and similar projects relates to SiC power device design, fabrication and testing.

The School of Engineering (SoE) at Warwick University (UoW) is the ideal place to carry out this kind of power electronics research. The University hosts the UK’s only industrial epitaxial SiC CVD reactor, a £2.6m facility, in an ISO class 4 cleanroom. Funded by EPSRC as part of the Centre for Power Electronics, the CVD reactor is used to grow the semiconductor layers of the device on the surface of the original SiC substrate (wafer). The facility can produce defect free, precisely controlled p- and n-doped SiC layers for use in high voltage blocking voltage devices. These materials are then characterised using UoW’s £24m materials and analytical sciences Research Technology Platform (RTP) with state-of-the-art electron microscopy, AFM and X-ray diffraction facilities. Its nationally unique facilities make the university one of very few institutions in Europe to house a dedicated SiC cleanroom, as well as an exhaustive list of simulation, packaging and characterisation facilities. The £3m state-of-the-art cleanroom is home annealing and oxidation furnaces, photolithography, TEOS SiO2 deposition, RIE/ICP etching, metal deposition and atomic layer deposition tools. At UoW a dedicated 10kV, 100A, parameter analyser is coupled to an automatic wafer prober. Alongside this, other more materials-specific techniques such as DLTS, uPCD, KOH etching and Hall measurement exist in a newly fabricated £300k “Wide Bandgap Semiconductor Characterisation Laboratory”.

Funding Notes

I welcome enquires at all times from suitable UK/EU candidates, which include anyone who has a minimum Bachelors degree of 2.1 (UK) or international equivalent qualifications. You should have an interest or experience in experimental engineering/chemistry/physics.
If you fit into this description, please read the areas of research below and contact me ([Email Address Removed]) with a CV to arrange an informal chat. Depending on the time of year, there may be other funding mechanisms ( available for UK/EU or international students; you are encouraged to search for these alongside making informal queries.
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