Quantum Computing (QC) is an emerging area of almost infinite excitement and potential. Whilst the vision for QC is decades old, recent years have seen a slew of breakthroughs in the design of practical QCs and the development of commercial and prototype systems from D-Wave, Rigetti Computing, IBM, Microsoft, Google and many others.
As the development of practical QCs continues apace, a series of fundamental QC architecture challenges arise. One of the most critical of these is the practical realisation of Quantum Error Correction (QEC) for detecting and correcting errors in the measured stated of QC qubits. This has a strong influence on the capacity of a quantum processor, by determining the proportion of the processor’s qubits given over to useful operations. This in turn influences the scale of workloads practical quantum processors can process. QEC is also a time-critical step in dynamic quantum operations, which demand state-dependent consideration of the next step in the evolution of a quantum program.
A very substantial body of work has investigated QEC approaches for their error detection and correction capability and, sometimes, complexity. But practical realisation has not been meaningfully considered in any substantive sense. In many cases the complexity and real-time constraints on the QEC process demand the use of Field Programmable Gate Array (FPGA) devices for practical realisation. There is almost no evidence of any attempt to realise practical QEC approaches on FPGA, nor consideration of QEC approaches in the context of FPGA realisation.
This project addresses this problem. It will develop the first practical FPGA solution for QEC of modern and medium-term quantum processors. This project is an Engineering and Physical Sciences Research Council (EPSRC) Doctoral Training Partnership (DTP) in conjunction with Keysight Technologies. It will be conducted in close cooperation with Keysight Technologies, as they develop their first line of FPGA-based quantum computer test equipment.
• To become familiar with the performance, complexity and implementation aspects of state-of-the-art QEC techniques.
• Analyse the suitability of existing algorithms for FPGA platforms
• Select a QEC approach for implementation and produce a realisation on Xilinx Virtex-Ultrascale FPGA.
• Characterise and optimise the accuracy/performance/cost design space of the solution from 3.
• Spend a minimum of three months across the course of the project on-site with Keysight Technologies adapting the technologies developed
• Present initial results in international data processing forums.
• Publish findings in IEEE journals.
A minimum 2.1 honours degree or equivalent in Electrical and Electronic Engineering, Computer Science, Mathematics, Physics or relevant degree is required. International English Language Testing System (IELTS) 6.0 with a minimum of 5.5 in all four elements of the test or equivalent.
This 3 ½ year PhD studentship, funded by the Engineering and Physical Science Research Council (EPSRC), commences 1 October 2019, subject to contract. It covers tuition fees and a maintenance grant (approximately £15,038 per annum), along with a top-up of £3,000 per year.
Applicants should apply electronically through the Queen’s online application portal at: https://dap.qub.ac.uk/portal/
Further information available at: http://www.qub.ac.uk/schools/eeecs/StudyattheSchool/PhDProgrammes
Supervisor Name: John McAllister
Tel: +44 (0)2890 971743
Email: [email protected]
Institute of Electronics, Communications and Information Technology (ECIT),
Deadline for submission of applications is 1st May 2019
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