About the Project
Co-supervisor Dr Graeme Bragg,
POETS (Partially Ordered Event Triggered Systems) technology is based on the idea of an extremely large number (millions) of small processing cores, embedded in a fast, bespoke, hardware, parallel communications infrastructure – the core mesh. Inter-core communication is asynchronous, and effected by small, fixed size, hardware data packets (a few bytes) – messages. For an important set of industrial problems, POETS architectures are capable of delivering orders of magnitude speed increases at significantly lower power levels
SpiNNaker (Spiking Neural Network Architecture) is a specialised computing engine, intended for real-time simulation of neural systems, and forms the basis of the project that led on to POETS. It consists of a mesh of 240x240 nodes, each containing 18 ARM9 processors: over a million cores, communicating via a bespoke network. Ultimately, the machine will support the simulation of up to a billion neurons in real time, allowing simulation experiments to be taken to hitherto unattainable scales. The architecture achieves this by ignoring three of the axioms of computer design: the communication fabric is non-deterministic; there is no global core synchronisation, and the system state - held in distributed memory - is not coherent. Time models itself: there is no notion of computed simulation time - wallclock time is simulation time. Whilst these design decisions are orthogonal to conventional wisdom, they bring the engine behaviour closer to its intended simulation target - neural systems. Whilst the SpiNNaker engine is a remarkable machine, it is based around ASIC technology, and so cannot be easily modified. It contains -quite deliberately - numerous design attributes that make it well-suited for its intended application domain - neural simulation, but which make it unsuitable for more general applications - hence POETS.
SpiNNaker contains within it a novel simulation algorithm, designed to deliver the response of large neural systems in real time. It interacts with the specialised hardware of SpiNNaker in ways that make it unsuitable for porting to conventional architectures, even if this were a desirable thing to do. However, POETS is derived from SpiNNaker - in the sense that both operate by the transmission of small packets - and the purpose of this project is to take the SpiNNaker simulation algorithm and transfer it to the POETS engine, with a view to comparing the performance of the two systems and perhaps being able to simulate even larger problems.
If you wish to discuss any details of the project informally, please contact Dr Graeme Bragg or Professor Andrew Brown or Professor John Chad, Sustainable Electronic Technologies (SET)Research Group, Email: [Email Address Removed] / [Email Address Removed] / [Email Address Removed] Tel: +44 (0) 2380 593374
A very good undergraduate degree (at least a UK 2:1 honours degree, or its international equivalent).
Closing date: applications should be received no later than 31 August 2020 for standard admissions, but later applications may be considered depending on the funds remaining in place.
Funding: This 3.5 year studentship covers UK tuition fees and provides an annual tax-free stipend at the standard EPSRC rate, which is £15,009 for 2019/20.
How To Apply
Applications should be made online here selecting “PhD Electronic and Electrical Engineering (Full time)” as the programme. Please enter Andrew Brown under the proposed supervisor.
For further information please contact: [Email Address Removed]
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