Supervisor: Prof Andrew Brown
Co-supervisor Dr Graeme Bragg
POETS - Partial Ordered Event Triggered Systems - technology is based on the idea of an extremely large number (millions) of small cores, embedded in a fast, bespoke, hardware, parallel communications infrastructure - the core mesh. Inter-core communication is asynchronous, and effected by small, fixed size, hardware data packets (a few bytes) - messages. For an important set of industrial problems, POETS architectures are capable of delivering orders of magnitude speed increases at significantly lower power levels. This project is about accelerating a simulation application using POETS.
Energy used by computing is currently estimated to account for 8% of the global electricity supply and recent predictions have suggested that datacentres will consume 20% by 2025. One way in which this problem is being addressed is through significant research into techniques for the management of contemporary multi-core and distributed HPC systems that reduce energy while maintaining application performance. Common techniques include, but are not limited to, power gating, where unused parts of a system are turned off to reduce static energy; task mapping, to efficiently use available hardware resources and facilitate other management techniques; and dynamic Voltage-frequency selection (DVFS), where the operating frequency and core voltage are varied during runtime to reduce dynamic energy.
State-of-the-art techniques can reduce the energy required to execute an application by upwards of 40% while significantly reducing idle power dissipation compared to using no management. Runtime management has also found its way into the consumer space with personal computers implementing DVFS by default and many mobile devices exploiting heterogeneous system architectures that mix energy-efficient and high-performance processing cores.
While the POETS architecture is intended to reduce power through its design, the application of management techniques that improve energy efficiency to achieve even greater savings of event-driven asynchronous many-core massively-parallel systems is a largely unexplored area that is essential to the ongoing maturation of these systems.
The objective of this project is to investigate and assess the applicability of existing state-of-the art system optimisation methods to POETS-like systems, which in turn will inform the design of novel optimisation methods.
If you wish to discuss any details of the project informally, please contact Dr Graeme Bragg or Professor Andrew Brown, Sustainable Electronic Technologies (SET)Research Group, Email: [email protected]
/ [email protected]
Tel: +44 (0) 2380 593374
A very good undergraduate degree (at least a UK 2:1 honours degree, or its international equivalent).
Closing date: applications should be received no later than 31 August 2020 for standard admissions, but later applications may be considered depending on the funds remaining in place.
Funding: This 3.5 year studentship covers UK tuition fees and provides an annual tax-free stipend at the standard EPSRC rate, which is £15,009 for 2019/20.
How To Apply
Applications should be made online here selecting “PhD Electrical and Electronic Engineering (Full time)” as the programme. Please enter Andrew Brown under the proposed supervisor.
Applications should include:
Two reference letters
Degree Transcripts to date
Apply online: https://www.southampton.ac.uk/courses/how-to-apply/postgraduate-applications.page
For further information please contact: [email protected]