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Security in Network-on-Chip interconnects


Department of Computer Science

About the Project

Research area: Autonomous and self-adaptive systems; Computer architectures; Cyber Physical Systems; Embedded systems;
Evolutionary computation; Real time languages and systems

Background
Multiprocessor platforms for real-time and embedded systems
Chips with multiple processing cores are already a reality in embedded systems, but there are many open issues on how to maximize system performance through parallelism while complying with constraints on chip area, cost, power consumption and heat dissipation. In order to find the best trade-off for each embedded application, developers must be able to validate the software functionality and performance over different alternatives of the hardware platform, and due to short time-to-market this is expected to be done even before the actual hardware is available.

Specific topic for PhD research:
Security in Network-on-Chip interconnects is a novel area of research, aiming to devise mechanisms that can make it harder for an attacker to obtain sensitive information by monitoring the behaviour of the NoC interconnect. The monitoring can be done by malicious applications using the NoC, or even by an external attacker using covert channels (e.g. temperature or electromagnetic activity). An important research question is to identify mechanisms that can improve NoC security without jeopardising performance guarantees, specially in the case of hard real-time applications.

References

L. S. Indrusiak, J. Harbin, and M. J. Sepulveda, Side-Channel Attack Resilience through Route Randomisation in Secure Real-Time Networks-on-Chip, arXiv:1607.03450 [cs.DC], 2016 (https://arxiv.org/abs/1607.03450).
M. J. Sepulveda, J.-P. Diguet, M. Strum, and G. Gogniat, NoC-Based Protection for SoC Time-Driven Attacks, IEEE Embedded Systems Letters, vol. 7, no. 1, pp. 7-10, Mar. 2015 (https://ieeexplore.ieee.org/document/6994256?arnumber=6994256&tag=1).
Y. Wang and G. E. Suh, Efficient Timing Channel Protection for On-Chip Networks, in: Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, Washington, DC, USA, 2012, pp. 142-151 (https://ieeexplore.ieee.org/document/6209273).

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