FindAPhD Weekly PhD Newsletter | JOIN NOW FindAPhD Weekly PhD Newsletter | JOIN NOW

TESiC-SuperJ: Trench and selective epitaxy for Silicon Carbide (SiC) superjunction devices

   School of Engineering

This project is no longer listed on and may not be available.

Click here to search for PhD studentship opportunities
  Dr V Shah  Applications accepted all year round  Funded PhD Project (UK Students Only)

About the Project

This studentship is associated with a recently funded £400k project (2021-2024) “TESiC-SuperJ - Trench Epitaxy for SiC Superjunctions” to create new Silicon Carbide materials for energy applications.

This studentship will be supervised by Dr Shah ( at the PEATER group at Warwick University (UK). The industrial partners on the project include LPE Spa, NovaSiC, Oxford Instruments Plasma Technology and Hitachi ABB Power Grids.

Superjunction (SJ) technology has the potential to revolutionise Silicon Carbide (SiC) power electronics, as it did for Silicon technology in the early 2000s. Early publications of SJ MOSFET device simulation demonstrate its advantages, demonstrating up to a 10x reduction in static losses compared to regular SiC MOSFETs of a similar rating. Yet, the fabrication methodology must be advanced if this is to become a mainstream technology. Conventional SJ construction in Silicon-only devices is accomplished through dopant diffusion but is not possible in SiC due to the material’s low diffusion coefficients. In this studentship, a fabrication methodology is to be developed involving the backfilling of trenches with epitaxy, which will not only enable the technology, but also reduce relative costs and fabrication steps compared to a diffusion-based approach. Using this methodology, these structures will be compatible with state of the art SiC mass production, allowing scaling for high current, advanced device testing and system integration.

Specifically in this studentship, a SiC trench refill method will be developed, in order to demonstrate a class of world-first, ≥6.5 kV SiC full-SJ power devices. The student will learn epitaxy, materials characterisation, device simulation and device fabrication. They will design experiments and process samples in our epitaxial and cleanroom facility, which includes state-of-the-art thin film deposition, atomic layer deposition, annealing furnaces, and lithographic facilities. They will also learn characterisation techniques such as electrical measurements (e.g. IV, CV, Hall measurement, DLTS, high voltage measurements), physical measurements (e.g. SEM, TEM, AFM, XRD). Indeed, they may also help to develop new characterisation techniques like c-AFM or XRT with partners or using national facilities (e.g. Diamond Light Source).

The PEATER group has built up a strong international reputation in the field of SiC power electronics for research, innovation and industrial collaboration. The group consists of 8 academics (including Dr Shah) whose research spans materials, devices fabrication, device simulation, packaging, reliability testing, gate driver and converter design, applications and even grid level research. The group are leaders of the Devices and Reliability Themes within the €6.77 million EPSRC Underpinning Power Electronics project. The group has had a wide portfolio of projects concerning SiC technology and device development, e.g. the £16m ESCAPE (from APC-12), £30m @Future BEV (from APC-15), SiCER (£300k, Innovate UK), HubNet (€6.5m), and VESI (€4.2) which are all concerned with SiC MOSFET and PiN diode development with breakdown voltage ranges from 3.3 kV to 10 kV and beyond. Within these projects, Dr Shah is developing growth and characterisation methodology for material suitable for >10 kV power devices. The accumulated knowledge from these and similar projects relates to SiC power device design, fabrication and testing.

The School of Engineering (SoE) at Warwick University (UoW) is the ideal place to carry out this kind of power electronics research. The University hosts the UK’s only industrial epitaxial SiC CVD reactor, a £2.6m facility, in an ISO class 4 cleanroom. Funded by EPSRC as part of the Centre for Power Electronics, the CVD reactor is used to grow the semiconductor layers of the device on the surface of the original SiC substrate (wafer). The facility can produce defect free, precisely controlled p- and n-doped SiC layers for use in high voltage blocking voltage devices. These materials are then characterised using UoW’s £24m materials and analytical sciences Research Technology Platform (RTP) with state-of-the-art electron microscopy, AFM and X-ray diffraction facilities. Its nationally unique facilities make the university one of very few institutions in Europe to house a dedicated SiC cleanroom, as well as an exhaustive list of simulation, packaging and characterisation facilities. The £3m state-of-the-art cleanroom is home annealing and oxidation furnaces, photolithography, TEOS SiO2 deposition, RIE/ICP etching, metal deposition and atomic layer deposition tools. At UoW a dedicated 10kV, 100A, parameter analyser is coupled to an automatic wafer prober. Alongside this, other more materials-specific techniques such as DLTS, uPCD, KOH etching and Hall measurement exist in a newly fabricated £300k “Wide Bandgap Semiconductor Characterisation Laboratory”.

Funding Notes

I welcome enquires at all times from suitable UK/EU candidates, which include anyone who has a minimum Bachelors degree of 2.1 (UK) or international equivalent qualifications. You should have an interest or experience in experimental engineering/chemistry/physics.
If you fit into this description, please read the areas of research below and contact me ([Email Address Removed]) with a CV to arrange an informal chat. Depending on the time of year, there may be other funding mechanisms available for UK/EU or international students (; you are encouraged to search for these alongside making informal queries.
Search Suggestions
Search suggestions

Based on your current searches we recommend the following search filters.

PhD saved successfully
View saved PhDs