It is widely recognised that variability in electronic device characteristics and the need to introduce novel device architectures both represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. The rapid increase in intrinsic parameter fluctuations, as devices get smaller, stemming from the fundamental discreteness of charge and matter and their statistical impact on device behaviour is a major source of device variability. The intrinsic parameter fluctuations are fundamental, truly stochastic and cannot be eliminated by tighter process control. The work in this research project, will study the impact of next generation technologies, and related parameter fluctuations, on the design of digital circuits using evolutionary computation. In particular we will attempt to determine answers to the following fundamental questions: How can evolutionary techniques be used within device models to alleviate parameter fluctuation problems? How can parameter variation datasets be best used by evolutionary techniques to improve system performance? How can evolutionary techniques be used to limit the effects of parameter variations?