Design and modeling of power-aware and variation-aware microprocessor architectures and circuits for IoT

The project focuses on innovative modeling and design solutions devoted to micro-processors (single and/or multi-core) subject to technology parameter variations and power efficiency stringent requirements, targeting IoT applications. Subjects of exploration may include, but will be not limited to, near-threshold micro-architectures and approximate computing implementation. General aspects that will be involved in the research activity include:
- circuit level (CMOS/FinFET) issues
- RTL design issues with FPGA or ASIC prototyping
- architecture level issues (cycle-accurate, instruction level simulations)

Required skills are digital circuit knowledge, microprocessors operation knowledge, VHDL, and C or C++ programming.

Facilities in the laboratory include device, circuit, RTL and architecture simulators, RTL synthesis tools, measurement instrumentation, FPGA prototyping tools and possibly access to silicon foundries if needed by the project. International cooperation with European and non-European research groups is expected.

CONTACT Prof. Mauro Olivieri for further information: [Email Address Removed] - SEE BELOW for application