Sub fJ/bit optical links using III-V compound semiconductor nanowires on silicon-on-insulator

In 2007, the International Technology Roadmap for Semiconductors (ITRS) published the requirements for 2020 energy-to-data efficiency requirements of 67 GHz. The upper limit of acceptable power dissipated from a chip is expected to saturate at 200 W, thus increased I/O rates must come at reduced energy per bit. The primary source of power dissipation is the ohmic loss of the electrical interconnect, accounting for ~ 80% of the dissipated power. Optical interconnects offer a potential solution for the tradeoff between power consumption and speed because the high carrier frequency (~200 THz) eliminates crosstalk, allowing multiple frequencies spaced around the carrier frequency to sum to a bit rate much higher than any individual channel. However, for on-chip optical links to be competitive there are stringent requirements, e.g., 1000 Tb/s. In this project, we will demonstrate an architecture to realize < 1 fJ/bit optical link based on both high quantum efficiency and efficiently coupled nanophotonic devices – the nanopillar array laser for the transmitter and plasmonically coupled single nanopillar photodiode for the receiver. High quality III-V material will be integrated on a SOI platform by MOCVD and/or MBE and novel photonic structures will be employed in order to realize the optical links.

The supervisor will direct a graduate student in the fabrication, characterization, and modeling of nanopillar-based photonic devices. The graduate student will learn the principles of state-of-the-art III-V compound semiconductor nanopillar growth on a SOI platform and CMOS fabrication technologies. Research staffs of the supervisors’ group will support research training with the opportunity to brainstorm new ideas and find creative solutions to a variety of challenges remained. The graduate student will also carry out detailed device simulations of nanopillar optoelectronics devices which include FDTD optical simulations and 3D drift diffusion modeling of injected and photogenerated carriers. Moreover, the graduate student will be offered a broad range of experiment opportunities for optoelectronic and photovoltaic applications beyond the III-V nanopillar growth. The high quality scientific challenges and close interaction with industrial partners such as Huawei and IQE will give the graduate student an excellent appreciation of the transferable skills.

Candidates should hold or expect to gain a first class degree or a good 2.1 and/or an appropriate Master’s level qualification (or their equivalent).

Applicants whose first language is not English will be required to demonstrate proficiency in the English language (IELTS 6.5 or equivalent)