Investigation into Reliability Enhancement of Three-dimensional Integrated Circuits

For more than five decades, Moore’s law has been the driving force of electronics design industry, which allowed shrinking the size of electronic devices by packing smaller and faster transistors in ICs. But due to physical limits of miniaturization, Moore’s law has been slowing down and is coming to an end. This will have an enormous impact on future technologies powered by high-end servers as well as handheld mobile computing devices. Researchers worldwide are searching for alternative solutions.

Three dimensional (3D) ICs have emerged as a promising technology that offers reduced power consumption, faster interconnects and smaller footprint than two dimensional (2D) ICs. 3D ICs consist of a stack of individual two-dimensional (2D) ICs, each of which is a silicon die, where through silicon vias (TSVs) are used as a vertical link for communication between different dies.

Despite potential advantages, one major obstacle to their widespread proliferation is insufficient understanding of reliability and test challenges. This is because manufacturing process introduces three new fabrication steps for 3D ICs: wafer thinning, alignment and bonding. These steps introduce new types of defects, which do not occur in existing fabrication processes for 2D ICs. New reliability challenges have emerged due to imperfect fabrication process, high thermal stress, inefficient thermal dissipation paths, PVT (process, voltage and temperature) variations and aging. At present, available reliability and test solutions provide limited capability. This research will advance the understanding of these failure mechanisms in 3D ICs and their control. It will address key challenges and deliver robust fault tolerant architectures and online design for test (DFT) methods, including rigorous validation to quantify and improve reliability and test.

This is novel research as currently there are only some initial works addressing these challenges. This thesis will address these key challenges and deliver robust solutions, including rigorous validation to quantify and improve reliability and test. Particular emphasis will be on co-optimisation of performance, power consumption and area overhead.

Candidate’s profile: Excellent GPA, knowledge of low power, high performance IC design. Excellent programming skills in C/C++ and familiarity with EDA tools (SPICE, Synopsys, Cadence etc.). Candidates with publications in reputed journals or international conferences will get preference.

For informal enquiries and more information, please email your updated CV (with GPA and list of publications) and statement of purpose to Dr Khursheed. at [Email Address Removed]