FULLY FUNDED Engineering Doctorate (EngD) in Large Scale Complex IT Systems (LSCITS): Real-Time Embedded Systems Scheduling, Verification and Visualisation, sponsored by Rapita Systems Ltd

Applications are invited for a Research Engineer to work on a research project in real-time scheduling, timing verification, and visualisation. The research project is fully funded and will be carried out in conjunction with studying for an Engineering Doctorate (EngD) in Large Scale Complex IT Systems (LSCITS). The Programme is a full time, 4-year doctoral level research degree involving a taught component, similar in scope to an MSc, and a research component requiring the Research Engineer to work closely with a sponsoring organisation.

This 4 year Engineering Doctorate project focuses on scheduling and timing behaviour verification and visualisation for large scale complex real-time embedded systems.

The project combines research into theory, algorithms and mechanisms for the scheduling of multiprocessor (multicore) and multi-criticality systems, with practical work on implementation, tracing, verifying, and visualising timing behaviour.

Size Weight and Power (SWaP) requirements are pushing developments in Avionics and Automotive Electronics towards the adoption of powerful embedded multicore processors. Combining different applications (often with different criticality levels) on the same multicore platform creates a host of interesting challenges and opportunities in addition to those present in single processor systems. For example, non-pre-emptive scheduling is used in many commercial embedded real-time applications. On single processors systems this form of scheduling ensures that tasks access shared resources in mutual exclusion; however, in multicore systems, two tasks running non-pre-emptively on different processors can still try to access shared resources at the same time, requiring the use of appropriate resource access protocols. Scheduling applications with different levels of criticality on a multiprocessor system provides an opportunity to do more with less, sharing processor bandwidth such that high criticality tasks are guaranteed sufficient processing time when required, yet low criticality tasks can utilise this bandwidth during normal operation.

In complex real-time systems, subtle and intermittent timing problems can result in significant costs as they often go undetected until late in the development lifecycle or worse are only revealed post deployment. Verification of timing behaviour therefore forms an important part of the testing process, while visualisation of the schedule, actual execution times of components, and resource accesses provides engineers with an effective means of understanding the behaviour of their system, and how subtle timing and memory access problems can arise.

The project will involve the design and development of prototype tools building upon Rapita Systems’ existing technology for trace data capture; measurement-based worst-case execution time analysis, code-coverage analysis, and visualisation (see www.rapitasystems.com).

The successful candidate will have a strong background in both software engineering and mathematics, an understanding of real-time systems, and good communication skills. Prior relevant commercial / industrial experience would be advantageous.

Applicants should be highly motivated and have a minimum of an upper second-class honours degree in Computer Science or related discipline (e.g. Electrical Engineering).